The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing a gate-all-around nanosheet field effect transistor having a self-limited inner spacer that provides source/drain isolation. The present application also provides a method of forming such a structure.
As semiconductor integrated circuits (ICs) or chips become smaller, vertically stacked semiconductor nanosheets, which are two-dimensional nanostructures in which the vertical thickness is substantially less than the width, are increasingly being used. Semiconductor nanosheets are seen as a feasible device option for 7 nm and beyond scaling of semiconductor devices. Vertically stacked semiconductor nanosheets provide area efficiency and can provide increased drive current within a given layout.
The general process flow for semiconductor nanosheet formation involves the formation of a material stack that contains alternating sacrificial semiconductor material nanosheets and semiconductor channel material nanosheets. After removing the sacrificial semiconductor material nanosheets, vertically stacked and suspended semiconductor channel material nanosheets are provided. A functional gate structure can be formed above and below each semiconductor channel material nanosheet to provide a gate-all-around design.
In the formation of semiconductor nanosheet containing devices, there is a need for providing an inner spacer for disconnecting the sacrificial layers from the epitaxy that forms the source/drain (S/D) semiconductor material structures. As scaling continues it is becoming more difficult to form inner spacers without pinch-off of the gate spacer to the gate spacer region.